Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same in which a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material.
A semiconductor memory device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). The data transfer occurs using a semiconductor property wherein an electrical conductivity changes depending on conditions. The transistor has three regions: a gate, a source, and a drain. Electric charges are moved between the source and the drain according to a control signal inputted to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region.
Where a general transistor is formed on a semiconductor substrate, a conventional method of forming a gate on the semiconductor substrate includes doping impurities into both sides of the gate to form a source and a drain. As the data storage capacity of semiconductor memory devices increases and the size of features decreases, the size of each unit cell also decreases. That is, a design rule of the capacitor and the transistor included in the unit cell has been reduced. Thus, while the channel length of a cell transistor is gradually decreased, the short channel effect, Drain Induced Barrier Lower (DIBL), etc., occur in a general transistor and thus operational reliability is decreased. By maintaining a threshold voltage such that the cell transistor performs a normal operation, it is possible to solve some of the problems caused by decreased channel length. In general, as the channel of the transistor shortens, the concentration of the impurities doped into a region in which the channel is formed has been increased.
However, if the concentration of the impurities doped into the channel region is increased while the design rule is reduced to 100 nm or less, the electric field of a Storage Node (SN) junction is increased, thereby lowering the refresh characteristics of a semiconductor memory device. In order to solve this problem, a cell transistor having a three-dimensional channel structure in which a channel extends in a vertical direction is used such that the channel length of the cell transistor is maintained even when the design rule is decreased. That is, even when a channel width in a horizontal direction is short, since the channel length of the vertical direction is secured, impurity doping concentration may be reduced and thus, refresh characteristics are maintained.
In addition, as the degree of integration of semiconductor devices is increased, the distance between a word line coupled to a cell transistor and a bit line coupled to the cell transistor is gradually reduced. As a result, there may arise shortcomings in which parasitic capacitance is increased such that an operating margin of a sense amplifier (sense-amp) that amplifies data transmitted via the bit line is deteriorated, resulting in a negative influence upon operation of the semiconductor device. In order to solve the above-mentioned shortcomings while simultaneously reducing parasitic capacitance between a bit line and a word line, a buried word line structure in which a word line is formed only in a recess instead of an upper part of the semiconductor substrate has been proposed. The buried word line structure includes a conductive material in a recess formed in a semiconductor substrate, and an insulation film covering an upper part of the conductive material such that the word line is buried in a semiconductor substrate. As a result, the buried word line structure can be electrically isolated from a bit line formed over a semiconductor substrate including source/drain regions.
However, the buried word line (buried gate) structure has some disadvantages. First, GIDL characteristics of a semiconductor device are deteriorated between a conductive material (gate electrode) and an N-type junction of an active region. Second, refresh characteristics of the whole semiconductor device are deteriorated due to the deteriorated GIDL characteristics.